VHDL源代碼：
?library ieee;????????????????????? --顯示器彩條發(fā)生器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity VGA is
?? port(clk,mode?? :in std_logic;??? --掃描時(shí)鐘/顯示模式選擇時(shí)鐘
??????? d,hs,vs,r,g,b:out std_logic);? --行，場(chǎng)同步/紅，綠，藍(lán)
end VGA;

architecture a of VGA is
??? signal hs1,vs1,fclk,cclk,divide_clk,dly:? std_logic;
??? signal mmode :std_logic_vector(1 downto 0);???? --方式選擇
??? signal cnt :std_logic_vector(2 downto 0);
??? signal fs :std_logic_vector(3 downto 0);
??? signal cc :std_logic_vector(4 downto 0);??????? --行同步/橫彩條生成
??? signal ll :std_logic_vector(8 downto 0);??????? --長(zhǎng)同步/豎彩條生成
??? signal grbh :std_logic_vector(3 downto 1);????? --X 橫彩條
??? signal grby :std_logic_vector(3 downto 1);????? --Y 豎彩條
??? signal grbx :std_logic_vector(3 downto 1);????? --文字
??? signal grbt :std_logic_vector(3 downto 1);????? --圖案
??? signal grbp :std_logic_vector(3 downto 1);?????
??? signal grb? :std_logic_vector(3 downto 1);
??? signal x :integer range 0 to 800;
??? signal x1: integer range 0 to 800;
??? signal y1: integer range 0 to 600;
??? signal x2: integer range 0 to 800;
??? signal x3: integer range 0 to 800;
??? signal x4: integer range 0 to 800;
??? signal x5: integer range 0 to 800;
??? signal x7: integer range 0 to 800;
??? signal x8: integer range 0 to 800;
??? signal x9: integer range 0 to 800;
??? signal x10: integer range 0 to 800;
??? signal x11: integer range 0 to 800;

??? signal y2: integer range 0 to 600;
??? signal y3: integer range 0 to 600;
??? signal y4: integer range 0 to 600;
??? signal y5: integer range 0 to 600;
??? signal y6: integer range 0 to 600;
??? signal c: integer range 0 to 30;