電子發燒友App
1、掌握TMS320LF2407 CAN控制器模塊的工作原理
2、掌握TMS320LF2407 CAN控制器模塊程序設計
;=======================================
* File name : REM_ANS.asm *
* Description : PROGRAM TO INITIATE AUTO–ANSWER TO A REMOTE FRAME *
* REQUEST IN CAN *
* The two CAN modules must be connected to each other with appropriate *
* termination resistors. Reception and transmission by MBX2. Low priority *
* interrupt used. Transmit acknowledge for MBX2 is set after running this *
* program and the message is transmitted.To be used along with REM_REQ.asm *
* PERIPHERAL CODE : A, TEST CODE : 0 After successful completion of *
* this program, the value A000 must be present in 3A0h (DM) *
* Error code:A001 –– Remote request not received from the remote node *
;======================================
.title ”REM_ANS” ; Title
.include “F2407REGS.H ” ; Variable and register declaration
.include “vectors.h” ; Vector label declaration
;––––––––––––––––––––––––––––––––––––––––––
; Constant definitions
;––––––––––––––––––––––––––––––––––––––––––
DP_PF1 .set 0E0h ; Page 1 of peripheral file (7000h/80h)
DP_CAN .set 0E2h ; CAN Register (7100h)
DP_CAN2 .set 0E4h ; CAN RAM (7200h)
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; M A C R O – Definitions
;––––––––––––––––––––––––––––––––––––––––––––––––
KICK_DOG .macro ; Watchdog reset macro
LDP #00E0h
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h
.endm
;=================================
; M A I N C O D E – starts here
;=========================
.text
START: SETC INTM ; Disable interrupts
LDP #DP_PF1
SPLK #0010h,SCSR1 ; Enable clock to CAN module
SPLK 06Fh,WDCR ; Disable Watchdog
KICK_DOG
LDP #7h ; Write error code to start with
SPLK #0A001h,020h ; at 3A0h in B1 memory
LDP #225
SPLK #00C0H,MCRB ; Configure CAN pins
LAR AR0,#300h ; AR0 => Copy CAN RAM (B0)
LAR AR1,#3h ; AR1 => counter
LAR AR2,#7214h ; AR2 => MBX2
;*************************************
; Enable 1 core interrupt
;**************************************
LDPK #0
SPLK #0000000000010000b, IMR ; core interrupt mask register
; | | | | | | | | | | | | | | | | |
;FEDCBA9876543210
SPLK #000ffh,IFR ; Clear all core interrupt flags
CLRC INTM ; enable interrupt
;****************************************
;******************** CAN Initialization***********************************
;********************************************
LDP #DP_CAN
SPLK #1001111111111110b,CANLAM1H ; Set LAM
SPLK #1111111111111111b,CANLAM1L ; 1:don’t care
SPLK #1011111111111111b,CANIMR ; Enable all interrupts
; bit 0 Warning level
; bit 1 Error passive
; bit 2 Bus off
; bit 3 Wake up
; bit 4 Write denied
; bit 5 Abort acknowledge
; bit 6 Receive message lost interrupt
; bit 7 Error interrupt priority level 1=low
; bit 8–D Mailbox interrupt mask
; bit E Reserved
; bit F Mailbox interrupt priority level. 1=low
;******************************************
;*********** Configure CAN before writing **********
;******************************************
LDP #DP_CAN
SPLK # 0000000000000000b,CANMDER
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–5 disable each mailbox
SPLK #0000000100000000b,CANMCR
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 8 CDR: Change data field request
;*****************************************
;*********** Write CAN Mailboxes **********
;**********************************************
LDP #DP_CAN2
SPLK #1111111111111111b,CANMSGID2H
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–12 upper 13 bits of extended identifier
; bit 13 Auto answer mode bit
; bit 14 Acceptance mask enable bit
; bit 15 Identifier extension bit
SPLK #1111111111111111b,CANMSGID2L
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–15 lower part of extended identifier
SPLK #0000000000001000b,CANMSGCTRL2
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–3 Data length code: 1000 = 8 bytes
; bit 4 0: data frame
SPLK #0BEBEh,CANMBX2A ; Message to be transmitted
SPLK #0BABAh,CANMBX2B ; to the remote node
SPLK #0DEDEh,CANMBX2C
SPLK #0DADAh,CANMBX2D
;***********************************************
;*********** Set parameters after writing **********
;*************************************************
LDP #DP_CAN
SPLK #0000000000000000b,CANMCR
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 8 CDR: Change data field request
SPLK #0000000000000100b,CANMDER
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–5 Enable MBX2
; bit 6 MBX2 configured as Transmit MBX
;*************************************************
;*********** CAN Registers configuration ***********************
;*********************************************************
SPLK #0001000000000000b,CANMCR
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 12 Change configuration request
W_CCE BIT CANGSR,#0Bh ; Wait for Change config Enable
BCND W_CCE,NTC
SPLK #0000000000000000b,CANBCR2
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–7 Baud rate prescaler
; bit 8–15 Reserved
SPLK #0000010101010111b,CANBCR1
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–2 TSEG1
; bit 3–6 TSEG2
; bit 7 Sample point setting (1: 3 times, 0: once)
; bit 8–A Synchronization jump width
; bit B Synchronization on falling edge
; bit C–F Reserved
SPLK #0000000000000000b,CANMCR
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 12 Change configuration request
W_NCCE BIT CANGSR,#0Bh ; Wait for Change config disable
BCND W_NCCE,TC
W_ERROR LACL CANESR ; Check errors
BCND W_ERROR,NEQ
LOOP B LOOP ; Wait for Receive Interrupt
;=======================================
; ISR used to copy MBX2 RAM when an interrupt is received
;=========================================
GISR5:
LOOP_READ MAR *,AR2
LACL *+,AR0 ; Copy MBX2 contents in Accumulator
SACL *+,AR1 ; Copy MBX2 contents in B0
BANZ LOOP_READ ; Copy all 4 words
LDP #7h ; Write A000 at 3A0h in B1 memory
SPLK #0A000h,020h ; if this ISR is executed once.
CLRC INTM
RET
PHANTOM RET
.end
; When data in MBX2 is transmitted in response to a ”Remote frame request,”
; the MBX2 data is copied from 300h onwards in DM. Note that TRS bit is not
; set for MBX2. The transmission of MBX2 data is automatic ,in response to
; a ”Remote frame request.”
;====================================
* File name : REM_REQ.asm *
* Description : PROGRAM TO TRANSMIT A REMOTE FRAME REQUEST IN THE CAN OF 240xA*
* The two CAN modules must be connected to each other with appropriate *
* termination resistors. Transmission of a remote frame by MBX3 and reception *
* of the data frame in MBX0. To be used along with REM_ANS.asm *
* PERIPHERAL CODE : A, TEST CODE : 0 After successful completion of *
* this program, the value A000 must be present in 3A0h (DM) *
* Error code:A001 –– Error in initialization/ communication *
;==================================
.title ”REM_REQ” ; Title
.include “ X2407.h” ; Variable and register declaration
.include “vectors”.h ; Vector label declaration
;––––––––––––––––––––––––––––––––––––––
; Other constant definitions
;––––––––––––––––––––––––––––––––––––
DP_PF1 .set 0E0h ; Page 1 of peripheral file (7000h/80h
DP_CAN .set 0E2h ; Can Registers (7100h)
DP_CAN2 .set 0E4h ; Can RAM (7200h)
;––––––––––––––––––––
; M A C R O – Definitions
;––––––––––––––––––––––––––
KICK_DOG .macro ; Watchdog reset macro
LDP #00E0h
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h
.endm
;===============================
; M A I N C O D E – starts here
;=========================================
.text
START: SETC INTM ; Disable interrupts
LDP #DP_PF1
SPLK #0010h,SCSR1 ; Enable clock to CAN module
SPLK 06Fh,WDCR ; Disable Watchdog
KICK_DOG
LDP #7h ; Write error code to start with
SPLK #0A001h,020h ; at 3A0h in B1 memory
LDP #225
SPLK #00C0H,MCRB ; Configure CAN pins
LAR AR0,#7204h ; AR0 => MBX0
LAR AR1,#300h ; AR1 => B0 RAM
LAR AR2,#3h ; AR2 => Counter
LAR AR3,#721ch ; AR3 => MBX3
;*********************************************
;******************** CAN Initialization***********************************
;**********************************************
LDP #DP_CAN
SPLK #1001111111111111b,CANLAM0H ; Set LAM0
SPLK #1111111111111111b,CANLAM0L ; 1:don’t care
SPLK #1011111111111111b,CANIMR ; Enable all interrupts
;*************************************************
;*********** Configure CAN before writing **********
;*********************************************************
LDP #DP_CAN
SPLK #0000000000000000b,CANMDER
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–5 disable each mailbox
SPLK #0000000100000000b,CANMCR
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 8 CDR: Change data field request
;*******************************************
;*********** Write CAN Mailboxes **********
;*****************************************
LDP #DP_CAN2
SPLK #1111111111111111b,CANMSGID3H
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–12 upper 13 bits of extended identifier
; bit 13 Auto answer mode bit
; bit 14 Acceptance mask enable bit
; bit 15 Identifier extension bit
SPLK #1111111111111111b,CANMSGID3L
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–15 lower part of extended identifier
SPLK #0000000000011000b,CANMSGCTRL3
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–3 Data length code. 1000 = 8 bytes
; bit 4 1: Remote frame
SPLK #1111111111111111b,CANMSGID0H
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–12 upper 13 bits of extended identifier
; bit 13 Auto answer mode bit
; bit 14 Acceptance mask enable bit
; bit 15 Identifier extension bit
SPLK #1111111111111110b,CANMSGID0L
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–15 lower part of extended identifier
SPLK #0000000000001000b,CANMSGCTRL0
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
;**********************************************
;*********** Set parameters after writing **********
;*************************************************
LDP #DP_CAN
SPLK #0000000000000000b,CANMCR
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 8 CDR: Change data field request
SPLK #0000000001001001b,CANMDER
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–5 enable mailbox 3 and mailbox 0
; bit 7 0: mailbox 3 = transmit
;*************************************************
;*********** CAN Registers configuration ***********************
;**********************************************************
SPLK #0001000000000000b,CANMCR
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 12 Change conf register
W_CCE BIT CANGSR,#0Bh ; Wait for Change config Enable
BCND W_CCE,NTC
SPLK #0000000000000000b,CANBCR2
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–7 Baud rate prescaler
; bit 8–15 Reserved
SPLK #0000010101010111b,CANBCR1
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 0–2 TSEG1
; bit 3–6 TSEG2
; bit 7 Sample point setting (1: 3 times, 0: once)
; bit 8–A Synchronization jump width
; bit B Synchronization on falling edge
; bit C–F Reserved
SPLK #0000000000000000b,CANMCR
;| | | | | | | | | | | | | | | | |
;FEDCBA9876543210
; bit 12 Change conf register
W_NCCE BIT CANGSR,#0Bh ; Wait for Change config disable
BCND W_NCCE,TC
;*******************************************
;*********** TRANSMIT **********
;**********************************************************
SPLK #0020h,CANTCR ; Transmit request for MBX3
W_TA BIT CANTCR,2 ; Wait for transmission acknowledge
BCND W_TA,NTC ; for MBX3
SPLK #2000h,CANTCR ; reset TA
RX_LOOP:
W_RA BIT CANRCR,BIT4 ; Wait for data from remote node
BCND W_RA,NTC ; to be written into MBX0
LOOP_READ2 MAR *,AR0 ; Copy MBX0 contents in Accumulator
LACL *+,AR1 ; Copy MBX0 contents in B0
SACL *+,AR2 ; Copy all 4 words
BANZ LOOP_READ2
LAR AR1,#300h ; AR1 => B0 RAM
MAR *,AR1
CHECK LACL *+ ; Check the received data
XOR #0BEBEh ; The remote node transmits
BCND LOOP,NEQ ; BEBEh , BABAh, DEDEh & DADAh
LACL *+ ;The correct reception of those
XOR #0BABAh ; 4 words are checked in this loop.
BCND LOOP,NEQ
LACL *+
XOR #0DEDEh
BCND LOOP,NEQ
LACL *+
XOR #0DADAh
BCND LOOP,NEQ
PASS LDP #7h ; Received data is correct
SPLK #0A000h,020h ; Write A000 in 3A0
LOOP B LOOP
PHANTOM RET
.end
工商網監
評論