--- 產品詳情 ---
Resolution (Bits) | 10 |
Number of channels (#) | 6 |
Samples/sec (MSPS) | 70 |
Supply voltage (Max) | 3.3 |
Operating temperature range (C) | 0 to 70 |
Output data format | LVDS |
- 3.3 V Single Supply Operation
- CDS or S/H Processing
- 35 MHz Channel Rate
- Enhanced ESD Protection on Timing, Control and LVDS Pins
- Low Power CMOS Design
- 12 Terminal to 16 Terminal (Selectable) LVDS Serialized Data Output
- 4–Wire Serial Interface
- 2 Channel Symmetrical Architecture
- Independent Gain and Offset Correction for Each Channel
- Digital Black Level Calibration for Each Channel
- Digital White Level Calibration for Each Channel
- Programmable Input Clamp
- Key Specifications
- Maximum Input Level:
- 1.2 Vp–p (CDS Gain = 1.0)
- 0.58 Vp–p (CDS Gain = 2.1)
- Input Sample Rate:
- 5 to 35 MSPS – 6ch mode
- 10 to 35 MSPS – 3ch mode
- PGA Gain Range: 1x to 10x (0 to 20 dB)
- CDS/SH Gain Settings: 1x or 2.1x
- Total Channel Gain: 1x to 21x (0 to 26 dB)
- PGA Gain Resolution: 8 bits – Analog
- ADC Resolution: 10 bits
- ADC Sampling Rate: 10 to 70 MSPS
- SNR: 68.5 dB (Gain = 1x)
- Offset DAC Range:
- ±111 mV or ±59.5 mV – FDAC
- ±281 mV – CDAC
- Offset DAC Resolution:
- ±10 bits – FDAC
- ±4 bits – CDAC
- Supply Voltage: 3.0 V to 3.6 V
- Power Dissipation: 1.02 W (typical)
- Maximum Input Level:
The LM98620 is a fully integrated, 10–Bit, 70 MSPS signal processing solution for high performance digital color copiers, scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative six channel architecture utilizing Correlated Double Sampling (CDS), or Sample and Hold (SH) type sampling. Gain settings of 1x or 2x are available in the CDS/SH input stage. Each channel has a dedicated 1x to 10x (8 bit) PGA that allows accurate gain adjustment. The Digital White Level auto calibration loop can automatically set the PGA value to achieve a selected white target level. Each channel also has a ±4 bit coarse and ±10 bit fine analog offset correction DAC that allows offset correction before the sample-and-hold amplifier. These correction values can be controlled by an automated Digital Black Level correction loop. The PGA and offset DACs for each channel are programmed independently allowing unique values of gain and offset for each of the six channels. A 2-to-1 multiplexing scheme routes the signals to three 70 MHz high performance ADCs. The fully differential processing channels achieve exceptional noise immunity, having a very low noise floor of –68.5dB. The 10 bit analog-to-digital converters have excellent dynamic performance, making the LM98620 transparent in the image reproduction chain.
為你推薦
-
TI數字多路復用器和編碼器SN54HC1512022-12-23 15:12
-
TI數字多路復用器和編碼器SN54LS1532022-12-23 15:12
-
TI數字多路復用器和編碼器CD54HC1472022-12-23 15:12
-
TI數字多路復用器和編碼器CY74FCT2257T2022-12-23 15:12
-
TI數字多路復用器和編碼器SN74LVC257A2022-12-23 15:12
-
TI數字多路復用器和編碼器SN74LVC157A2022-12-23 15:12
-
TI數字多路復用器和編碼器SN74ALS258A2022-12-23 15:12
-
TI數字多路復用器和編碼器SN74ALS257A2022-12-23 15:12
-
TI數字多路復用器和編碼器SN74ALS157A2022-12-23 15:12
-
TI數字多路復用器和編碼器SN74AHCT1582022-12-23 15:12
-
電動汽車直流快充方案設計【含參考設計】2023-08-03 08:08
-
Buck電路的原理及器件選型指南2023-07-31 22:28
-
100W USB PD 3.0電源2023-07-31 22:27
-
基于STM32的300W無刷直流電機驅動方案2023-07-06 10:02
-
上新啦!開發板僅需9.9元!2023-06-21 17:43
-
參考設計 | 2KW AC/DC數字電源方案2023-06-21 17:43
-
千萬不能小瞧的PCB半孔板2023-06-21 17:34