研究了C8051 微控制器IP 軟核的參數化設計。首先介紹了指令系統的設計，其次從可重
配置的存儲器容量、可取舍的并行輸入/輸出端口、是否產生UART 和定時/計數器模塊，以及可重配置的乘法器等幾個方面進行了參數化的設計，最后介紹了在不同功能參數配置下的仿真驗證、綜合結果及延時分析。參數化設計方法增強了IP 軟核在SoC 應用中的可配置性和可重用性。
關鍵詞：微控制器；軟核；可配置性；可重用性
Abstract: The parameterized design about the C8051 micro controller IP soft core is studied. Firstly, he design of the instruction system is introduced. Secondly, from the reconfigurable capacitance of emory, parallel input/output port, UART and timer/counter which can be accepted or rejected, and he reconfigurable multiplier, the detailed method for the C8051 micro controller IP soft core about arameterized design is described. Finally, the verification of simulation, the result of synthesis and he delay analysis using different configurable parameters are introduced. The parameterized design ethod enhances the reconfigurable and reusable of IP soft core in the field of System on Chip design.
Key Words: micro controller; soft core; reconfigurable; reusable